Suppose the functions F and G can be computed in 5 and 3 nanoseconds by functional units UF and UG, respectively. Given two instances of UF and two instances of UG, it is required to implement the computation [G16S2Q40]

Explanation

Consider a processor with 64 registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and a twelve-bit immediate value [G16S2Q41]

Explanation

A processor can support a maximum memory of 4 GB, where the memory is word-addressable (a word consists of two bytes). The size of the address bus of the processor is at least bits. [G16S1Q19]

Explanation

Match the following : [G17S2Q2]

Explanation

The n-bit fixed-point representation of an unsigned real number X uses f bits for the fraction part. Let i=n-f. The range of decimal values for X in this representation is [G17S1Q7]

Explanation

When two 8-bit numbers A7...A0 and B7...B0 in 2's complement representation (with A0 and B0 as the least significant bits) are added using a ripple-carry adder, the sum bits obtained are S1....S0 and the carry bits are c7....C0. An overflow is said to have occurred if [G17S1Q9]

Explanation

consider the following intermediate program in three address code [G17S1Q12]

Explanation

Consider a RISC machine where each instruction is exactly 4 bytes long. Conditional and unconditional branch instructions use PC-relative addressing mode with Offset specified in bytes to the target location [G17S1Q49]

Explanation

Instruction execution in a processor is divided into 5 stages. Instruction Fetch (IF), Instruction Decode(ID), Operand Fetch(OF), Execute(EX), and Write Back(WB). [G17S1Q50]

Explanation

Consider the expression (a-1)*(((b+c)/3)+d)). Let X be the minimum number of registers required by an optimal code generation [G17S1Q52]

Explanation