Consider an eight-bit ripple-carry adder for computing the sum of A and B, where A and B are integers represented in 2’s complement form. If the decimal value of A is one, the decimal value of B that leads to the longest latency for the sum to stabilize is [G16S2Q17]

Explanation

Let, x1⊕x2⊕x3⊕x4 = 0 where x1, x2, x3, x4 are Boolean variables, and ⊕ is the XOR operator. Which one of the following must always be TRUE? [G16S2Q18]

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Let X be the number of distinct 16-bit integers in 2’s complement representation. Let Y be the number of distinct 16-bit integers in sign magnitude representation. Then X −Y is [G16S2Q19]

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A processor has 40 distinct instructions and 24 general purpose registers. A 32-bit instruction word has an opcode, two register operands and an immediate operand. The number of bits available for the immediate operand field is [G16S2Q20]

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The 16-bit 2’s complement representation of an integer is 1111 1111 1111 0101; its decimal representation is . [G16S1Q17]

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We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is [G16S1Q18]

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Consider the two cascaded 2-to-1 multiplexers as shown in the figure [G16S1Q40]

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The size of the data count register of a DMA controller is 16 bits. The processor needs to transfer a file of 29,154 kilobytes from disk to main memory. [G16S1Q41]

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The stage delays in a 4-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. [G16S1Q42]

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Consider a carry lookahead adder for adding two n-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is [G16S1Q43]

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Given f(w,x,y,z) = [G17S2Q28]

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The next state table of a 2-bit saturating up-counter is given below. [G17S2Q42]

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The general configuration of the microprogrammed control unit is given below : [J17P3Q3]

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Match the following : [J17P3Q4]

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Consider the Karnaugh map given below, where x represents "don'tcare" and blank represents 0. [G17S1Q21]

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Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and the out of the T flip-flop is connected to the input of the D flip-flop [G17S1Q33]

Explanation

Which of the following addressing mode is best suited to access elements of an array of contiguous memory locations ? [N17P3Q4]

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Which of the following is correct statement ? [N17P3Q5]

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